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74ALVCH16600DGG:11

IC UNIV BUS TXRX 18BIT 56TSSOP

Product Category: Universal Bus Functions
Mfr. Part #
74ALVCH16600DGG:11
Manufacturer: NXP Semiconductors
Package: 56-TFSOP (0.240", 6.10mm Width)
Lead Free Status /RoHS Status:
Data Sheet: 74ALVCH16600DGG:11 Datasheet
Inventory: In Stock

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Mfr. Part #: 74ALVCH16600DGG:11

Specifications
Product Details

Specifications

Manufacturer NXP Semiconductors

Product Category Universal Bus Functions

Series 74ALVCH

Product CMOS

Packaging Tape & Reel (TR) Alternate Packaging

Unit-Weight 0.026103 oz

Mounting-Style SMD/SMT

Package-Case 56-TFSOP (0.240", 6.10mm Width)

Operating-Temperature -40Â°C ~ 85Â°C

Mounting-Type Surface Mount

Output-Type 3-State

Function Universal Bus Transceiver

Number-of-Channels 18 Channels

Voltage-Supply 2.3 V ~ 3.6 V

Supplier-Device-Package 56-TSSOP

Number-of-Circuits 18-Bit

Number-of-Inputs -

Current-Output-High-Low 24mA, 24mA

Logic-Type Universal Bus Transceiver

Maximum Operating Temperature + 85 C

Operating temperature range - 40 C

Polarity Non-Inverting

Supply-Current-Max 40 uA

Part-#-Aliases 74ALVCH16600DG-T

Supply-Voltage-Max 3.6 V

Supply-Voltage-Min 2.3 V

Package-Case TSSOP-56

Logic-Family ALVC

Propagation Delay 2.9 ns

Output-Level LVTTL

Input-Level LVTTL

High-Level-Output-Current - 24 mA

Low-Level-Output-Current 24 mA

Product Details

DESCRIPTION

The 74ALVCH16600 is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is High. When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the High-to-Low transition of CPAB. When OEAB is Low, the outputs are active. When OEAB is High, the outputs are in the high-impedance state. The High clock can be controlled with the clock-enable inputs (CEBA/CEAB).

FEATURES

â€¢ Complies with JEDEC standard no. 8-1A.
â€¢ CMOS low power consumption
â€¢ Direct interface with TTL levels
â€¢ Current drive Â± 24 mA at 3.0 V
â€¢ All inputs have bus hold circuitry
â€¢ Output drive capability 50â„¦ transmission lines @ 85Â°C
â€¢ MULTIBYTETM flow-through standard pin-out architecture
â€¢ Low inductance multiple VCC and ground pins for minimum noise and ground bounce

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Mfr. Part #: 74ALVCH16600DGG:11