8CPLC2048LTXI

Features

â–  Powerline Communication Solution
❐ Integrated Powerline Modem PHY
❐ Frequency Shift Keying Modulation
❐ Configurable baud rates up to 2400 bps
❐ Powerline Optimized Network Protocol
❐ Integrates Data Link, Transport, and Network Layers
❐ Supports Bidirectional Half Duplex Communication
❐ 8-bit CRC Error Detection to Minimize Data Loss
❐ I2C enabled Powerline Application Layer
❐ Supports I2C Frequencies of 50, 100, and 400 kHz
❐ Reference Designs for 110V/240V AC and 12V/24V AC/DC Powerlines
❐ Reference Designs comply with CENELEC EN 50065-1:2001 and FCC Part 15
â–  Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ Two 8x8 Multiply, 32-Bit Accumulate
■ Programmable System Resources (PSoC® Blocks)
❐ 12 Rail-to-Rail Analog PSoC Blocks provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ 16 Digital PSoC Blocks provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Up to Four Full Duplex UARTs
• Multiple SPITM Masters or Slaves
• Connectable to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
â–  Flexible On-Chip Memory
❐ 32 KB Flash Program Storage 50,000 Erase or Write Cycles
❐ 2 KB SRAM Data Storage
❐ EEPROM Emulation in Flash
â–  Programmable Pin Configurations
❐ 25 mA Sink, 10 mA Source on all GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on all GPIO
❐ Up to 12 Analog Inputs on GPIO
❐ Configurable Interrupt on all GPIO
â–  Additional System Resources
❐ I2C Slave, Master, and Multi-Master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
â–  Complete Development Tools
❐ Free Development Software (PSoC Designer™)
❐ Full Featured In-Circuit Emulator (ICE) and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128 KB Trace Memory
❐ Complex Events
❐ C Compilers, Assembler, and Linker