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EPC1213LC20

212kb Flash SMD/SMT 0Â°C ~ 70Â°C OTP EPC 20-PLCC (9x9) 4.75 V ~ 5.25 V

Product Category: FPGA - Field Programmable Gate Array Chips
Mfr. Part #
EPC1213LC20
Manufacturer: Intel / Altera
Package: 20-LCC (J-Lead)
Lead Free Status /RoHS Status:
Data Sheet: EPC1213LC20 Datasheet
Inventory: In Stock

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Mfr. Part #: EPC1213LC20

Specifications
Product Details

Specifications

Manufacturer Intel / Altera

Product Category Configuration Proms for FPGAs

Series EPC

Packaging Tube

Unit-Weight 0.025468 oz

Mounting-Style SMD/SMT

Tradename Enpirion

Package-Case 20-LCC (J-Lead)

Operating-Temperature 0Â°C ~ 70Â°C

Voltage-Supply 4.75 V ~ 5.25 V

Supplier-Device-Package 20-PLCC (9x9)

Memory Capacity 212kb

Memory-Type Flash

Programmable-Type OTP

Maximum Operating Temperature + 70 C

Operating temperature range 0 C

Operating-Supply-Current 100 uA

Maximum-Operating-Frequency 6 MHz

Supply-Voltage-Max 5.25 V

Supply-Voltage-Min 4.75 V

Package-Case PLCC-20

Product Details

Functional Description

With SRAM-based devices, configuration data must be reloaded each time the device powers up, the system initializes, or when new configuration data is needed. Altera configuration devices store configuration data for SRAM-based ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices.

Features

Configuration devices for SRAM-based LUT devices offer the following features:
â– Configures Altera ACEXÂ® 1K, APEXÂ® 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, ArriaÂ® GX, CycloneÂ®, Cyclone II, FLEXÂ® 10K (including FLEX 10KE and FLEX 10KA) MercuryÂ®, StratixÂ®, Stratix GX, Stratix II, and Stratix II GX devices
â– Easy-to-use four-pin interface
â– Low current during configuration and near-zero standby mode current
â– Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers
â– Available in compact plastic packages
â– 8-pin plastic dual in-line (PDIP) package
â– 20-pin plastic J-lead chip carrier (PLCC) package
â– 32-pin plastic thin quad flat pack (TQFP) package
â– EPC2 device has reprogrammable flash configuration memory
â– 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.
1149.1 JTAG interface
â– Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
â– Supports programming through Serial Vector Format File (.svf), Jamïƒ” Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartusïƒ’ II and MAX+PLUSïƒ’ II softwares using the USB-Blasterïƒ”, MasterBlasterÂ®, ByteBlasterÂ® II, EthernetBlaster, or ByteBlasterMVÂ® download cable
â– Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices
â– nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration

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Mfr. Part #: EPC1213LC20