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EPC2LC20N

10 MHz 1.6Mb 0Â°C ~ 70Â°C Tube In System Programmable EPC 20-PLCC (9x9) 3 V ~ 3.6 V, 4.75 V ~ 5.25 V

Product Category: Integrated Circuits (IC Chips)
Mfr. Part #
EPC2LC20N
Manufacturer: Intel / Altera
Package: 20-LCC (J-Lead)
Lead Free Status /RoHS Status:
Data Sheet: EPC2LC20N Datasheet
Inventory: In Stock

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Mfr. Part #: EPC2LC20N

Specifications
Product Details

Specifications

Manufacturer Intel / Altera

Product Category Memory - Configuration Proms for FPGA's

Series EPC

Packaging Tube

Unit-Weight 0.025468 oz

Mounting-Style SMD/SMT

Tradename Enpirion

Package-Case 20-LCC (J-Lead)

Operating-Temperature 0Â°C ~ 70Â°C

Voltage-Supply 3 V ~ 3.6 V, 4.75 V ~ 5.25 V

Supplier-Device-Package 20-PLCC (9x9)

Memory Capacity 1.6Mb

Memory-Type Flash

Programmable-Type In System Programmable

Maximum Operating Temperature + 70 C

Operating temperature range 0 C

Operating-Supply-Current 50 uA

Maximum-Operating-Frequency 10 MHz

Supply-Voltage-Max 5.25 V

Supply-Voltage-Min 3 V

Package-Case PLCC-20

Product Details

EPC2LC20N Description

FPGA - Configuration Memory IC - Ser. Config Mem Flash 1.6Mb 10 MHz

EPC2LC20N Features

Configuration devices for SRAM-based LUT devices offer the following features:
â– Configures Altera ACEXïƒ’ 1K, APEXïƒ” 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arriaïƒ’ GX, Cycloneïƒ’, Cyclone II, FLEXïƒ’ 10K (including FLEX 10KE and FLEX 10KA) Mercuryïƒ”, Stratixïƒ’, Stratix GX, Stratix II, and Stratix II GX devices
â– Easy-to-use four-pin interface
â– Low current during configuration and near-zero standby mode current
â– Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers
â– Available in compact plastic packages
â– 8-pin plastic dual in-line (PDIP) package
â– 20-pin plastic J-lead chip carrier (PLCC) package
â– 32-pin plastic thin quad flat pack (TQFP) package
â– EPC2 device has reprogrammable flash configuration memory
â– 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.
1149.1 JTAG interface
â– Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
â– Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable
â– Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices
â– nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration

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Mfr. Part #: EPC2LC20N