EPC2LI20N

EPC2LI20N Description

With SRAM-based devices, configuration data must be reloaded each time the device powers up, the system initializes, or when new configuration data is needed. Altera configuration devices store configuration data for SRAM-based ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices.

EPC2LI20N Features

â–  Configures Altera ACEX® 1K, APEX® 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria® GX, Cyclone®, Cyclone II, FLEX® 10K (including FLEX 10KE and FLEX 10KA) Mercury®, Stratix®, Stratix GX, Stratix II, and Stratix II GX devices
â–  Easy-to-use four-pin interface
â–  Low current during configuration and near-zero standby mode current
â–  Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers
â–  Available in compact plastic packages
â–  8-pin plastic dual in-line (PDIP) package
â–  20-pin plastic J-lead chip carrier (PLCC) package
â–  32-pin plastic thin quad flat pack (TQFP) package
â–  EPC2 device has reprogrammable flash configuration memory
â–  5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.
1149.1 JTAG interface
â–  Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
â–  Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster, MasterBlaster®, ByteBlaster® II, EthernetBlaster, or ByteBlasterMV® download cable
â–  Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices
â–  nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration

EPC2LI20N Applications

â– Data acquisition and interface logic areas
â– Communication systems
â– Digital signal processing