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EPM7128SLC84-6

IC CPLD 128MC 6NS 84PLCC

Product Category: Touch Screen Controllers
Mfr. Part #
EPM7128SLC84-6
Manufacturer: Intel / Altera
Package: 84-LCC (J-Lead)
Lead Free Status /RoHS Status:
Data Sheet: EPM7128SLC84-6 Datasheet
Inventory: In Stock

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Mfr. Part #: EPM7128SLC84-6

Specifications
Product Details

Specifications

Manufacturer Intel / Altera

Product Category Touch Screen Controllers

Series MAXÂ® 7000S

Product MAX 7000

Packaging Tray

Unit-Weight 0.239083 oz

Mounting-Style SMD/SMT

Tradename MAX 7000

Package-Case 84-LCC (J-Lead)

Operating-Temperature 0Â°C ~ 70Â°C (TA)

Mounting-Type Surface Mount

Supplier-Device-Package 84-PLCC (29.31x29.31)

Memory-Type EEPROM

Programmable-Type In System Programmable

Delay-Time-tpd-1-Max 6.0ns

Voltage-Supply-Internal 4.75 V ~ 5.25 V

Number-of-Logic-Elements-Blocks 8

Number-of-Macrocells 128 Macrocells

IC Number of Gates 2500

Number-of-I-O 68 I/O

Maximum Operating Temperature + 70 C

Operating temperature range 0 C

Operating-Supply-Voltage 3.3 V

Maximum-Operating-Frequency 147.1 MHz

Supply-Voltage-Max 3.6 V

Supply-Voltage-Min 3 V

Package-Case PLCC-84

Propagation-Delay-Max 6 ns

Input/output 68 I/O

Number-of-Logic-Array-Blocks-LABs 8

Product Details

Description

The MAX 7000 family of high-density, high-performance PLDs is based on Alteraâ€™s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP,pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3 for available speed grades.

Features

â– High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAXÂ®architecture
â– 5.0-V in-system programmability(ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
â€“ ISP circuitry compatible with IEEE Std. 1532
â– Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
â– Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells
â– Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1and 2)
â– 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)
â– PCI-compliant devices available

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Mfr. Part #: EPM7128SLC84-6