OR4E6-FPGA-EV

Product Description

Architecture Overview
The ORCA Series 4 architecture is a new generation of SRAM-based programmable devices from Lucent Technologies Microelectronics Group. It includes enhancements and innovations geared toward today’s high-speed systems on a single chip. Designed with networking applications in mind, the Series 4 family incorporates system-level features that can further reduce logic requirements and increase system speed. ORCA Series 4 devices contain many new patented enhancements and are offered in a variety of packages and speed grades.

Programmable Features

â–  High-performance platform design.
— 0.13 µm seven-level metal technology.
— Internal performance of >250 MHz (four logic levels).
— I/O performance of >416 MHz for all user I/Os.
— Over 1.5 million usable system gates.
— Meets multiple I/O interface standards.
— 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance.
— Embedded block RAM (EBR) for onboard storage and buffer needs.
— Built-in system components including an internal system bus, eight PLLs, and microprocessor interface.
â–  Traditional I/O selections.
— LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V) I/Os.
— Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance.
— Individually programmable drive capability. 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source.
— Two slew rates supported (fast and slew-limited).
— Fast-capture input latch and input flip-flop (FF)/ latch for reduced input setup time and zero hold time.
— Fast open-drain drive capability.
— Capability to register 3-state enable signal.
— Off-chip clock drive capability.
— Two-input function generator in output path.
â–  New programmable high-speed I/O.
— Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I & II), HSTL (Class I, III, IV), zero-bus turn-around (ZBT*), and double data rate (DDR).
— Double-ended: LDVS, bused-LVDS, LVPECL.
— Customer defined: Ability to substitute arbitrary standard-cell I/O to meet fast moving standards.
â–  New capability to (de)multiplex I/O signals.
— New DDR on both input and output at rates up to 311 MHz (622 MHz effective rate).
— Used to implement emerging RapidIO† backplane interface specification.
— New 2x and 4x downlink and uplink capability per I/O (i.e., 104 MHz internal to 416 MHz I/O).
â–  Enhanced twin-quad programmable function unit (PFU).
— Eight 16-bit look-up tables (LUTs) per PFU.
— Nine user registers per PFU, one following each LUT and organized to allow two nibbles to act independently, plus one extra for arithmetic carry/borrow operations.
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