PCA95BS118

General description

The PCA9574 is a CMOS device that provides 8 bits of General Purpose parallel Input/Output (GPIO) expansion in low voltage processor and handheld battery powered mobile applications and was developed to enhance the NXP family of I2C-bus I/O expanders. The improvements include lower supply current, lower operating voltage of 1.1 V to 3.6 V, dual and separate supply rails to allow voltage level translation anywhere between 1.1 V and 3.6 V, 400 kHz clock frequency, and smaller packaging. Any of the 8 I/O ports can be configured as an input or output independent of each other and default on start-up to inputs. I/O expanders provide a simple solution when additional I/Os are needed while keeping interconnections to a minimum; for example in battery powered mobile applications and clamshell devices for interfacing to sensors, push buttons, keypad, etc. In addition to providing a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage level to I/O devices operating at a different (usually higher) voltage level. PCA9574 has built-in level shifting feature that makes these devices extremely flexible in mixed signal environments where communication between incompatible I/Os is required. The core of PCA9574 can operate at a voltage as low as 1.1 V while the I/O bank can operate in the range 1.1 V to 3.6 V. Bus hold with programmable on-chip pull-up or pull-down feature for I/Os is also provided.

Features

â–  400 kHz I2C-bus serial interface
â–  Compliant with I2C-bus Standard-mode (100 kHz)
â–  Separate supply rails for core logic and I/O bank provides voltage level shifting
â–  1.1 V to 3.6 V operation with level shifting feature
■ Very low standby current: < 1 µA
â–  8 configurable I/O pins that default to inputs at power-up
â–  Outputs:
♦ Totem pole: 1 mA source and 3 mA sink
♦ Independently programmable 100 kΩ pull-up or pull-down for each I/O pin
♦ Open-drain active LOW interrupt (INT) output pin allows monitoring of logic level change of pins programmed as inputs
â–  Inputs:
♦ Programmable bus hold provides valid logic level when inputs are not actively driven
♦ Programmable Interrupt Mask Control for input pins that do not require an interrupt when their states change or to prevent spurious interrupts default to mask at power-up
♦ Polarity inversion register allows inversion of the polarity of the I/O pins when read
â–  Active LOW reset (RESET) input pin resets device to power-up default state
â–  GPIO All Call address allows programming of more than one device at the same time with the same parameters
â–  2 programmable slave addresses using 1 address pin
■ −40 °C to +85 °C operation
â–  ESD protection exceeds 7000 V HBM per JESD22-A114, 500 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
â–  Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
â–  Packages offered: TSSOP16, HVQFN16 and HXQFN16U

Applications

â–  Cell phones
â–  Media players
â–  Multi voltage environments
â–  Battery operated mobile gadgets
â–  Motherboards
â–  Servers
â–  RAID systems
â–  Industrial control
â–  Medical equipment
â–  PLCs