PCA9616PW118

General description

The PCA9617A is a CMOS integrated circuit that provides level shifting between low voltage (0.8 V to 5.5 V) and higher voltage (2.2 V to 5.5 V) Fast-mode Plus (Fm+) I2C-bus or SMBus applications. While retaining all the operating modes and features of the I2C-bus system during the level shifts, it also permits extension of the I2C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 540 pF at 1 MHz or up to 4000 pF at lower speeds. Using the PCA9617A enables the system designer to isolate two halves of a bus for both voltage and capacitance. The SDA and SCL pins are overvoltage tolerant and are high-impedance when the PCA9617A is unpowered.

Features and benefits

â–  2 channel, bidirectional buffer isolates capacitance and allows 540 pF on either side of
the device at 1 MHz and up to 4000 pF at lower speeds
â–  Voltage level translation from 0.8 V to 5.5 V and from 2.2 V to 5.5 V
â–  Footprint and functional replacement for PCA9517A at Fast-mode speeds
â–  Port A operating supply voltage range of 0.8 V to 5.5 V with normal levels
â–  Port B operating supply voltage range of 2.2 V to 5.5 V with static offset level
â–  5 V tolerant I2C-bus and enable pins
â–  0 Hz to 1000 kHz clock frequency (the maximum system operating frequency may be
less than 1000 kHz because of the delays added by the repeater)
â–  Active HIGH repeater enable input referenced to VCC(B)
â–  Open-drain input/outputs
â–  Latching free operation
â–  Supports arbitration and clock stretching across the repeater
â–  Accommodates Standard-mode, Fast-mode and Fast-mode Plus I2C-bus devices,
SMBus (standard and high power mode), PMBus and multiple masters
â–  Powered-off high-impedance I2C-bus pins
â–  ESD protection exceeds 5500 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
â–  Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
â–  Packages offered: TSSOP8 and HWSON8