PEF20525FV1.3

Introduction

The SEROCCO-H is a Serial Communication Controller with two independent serial channels1). The serial channels are derived from updated protocol logic of the ESCC and DSCC4 device family providing a large set of protocol support and variety in serial interface configuration. This allows easy integration to different environments and applications.

Features

Serial communication controllers (SCCs)
• Two independent channels
• Full duplex data rates on each channel of up to 12.5 Mbit/s sync - 2 Mbit/s with DPLL
• 64 Bytes deep receive FIFO per SCC
• 64 Bytes deep transmit FIFO per SCC

Serial Interface

• On-chip clock generation or external clock sources
• On-chip DPLLs for clock recovery
• Baud rate generator
• Clock gating signals
• Clock gapping capability
• Programmable time-slot capability for connection to TDM interfaces (e.g. T1, E1)
• NRZ, NRZI, FM and Manchester data encoding
• Optional data flow control using modem control lines (RTS, CTS, CD)
• Support of bus configuration by collision detection and resolution

Bit Processor Functions

• HDLC/SDLC Protocol Modes
– Automatic flag detection and transmission
– Shared opening and closing flag
– Generation of interframe-time fill ’1’s or flags
– Detection of receive line status
– Zero bit insertion and deletion
– CRC generation and checking (CRC-CCITT or CRC-32)
– Transparent CRC option per channel and/or per frame
– Programmable Preamble (8 bit) with selectable repetition rate
– Error detection (abort, long frame, CRC error, short frames)
• Bit Synchronous PPP Mode
– Bit oriented transmission of HDLC frame (flag, data, CRC, flag)
– Zero bit insertion/deletion
– 15 consecutive ’1’ bits abort sequence
• Octet Synchronous PPP Mode
– Octet oriented transmission of HDLC frame (flag, data, CRC, flag)
– Programmable character map of 32 hard-wired characters (00H-1FH)
– Four programmable characters for additional mapping
– Insertion/deletion of control-escape character (7DH) for mapped characters
• Extended Transparent Mode
– Fully bit transparent (no framing, no bit manipulation)
– Octet-aligned transmission and reception
• Protocol and Mode Independent
– Data bit inversion
– Data overflow and underrun detection
– Timer
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