SI5315A-C-GM

Description

The Si5315 is a jitter-attenuating clock multiplier for Gb and 10G Synchronous Ethernet, SONET/SDH, and PDH (T1/E1) applications. The Si5315 supports SyncE EEC options 1 and 2 when paired with a timing card that implements the required wander filter. The Si5315 accepts dual clock inputs ranging from 8 kHz to 644.53 MHz and generates two equal frequency-multiplied clock outputs ranging from 8 kHz to 644.53 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SyncE and T1/E1 rates. The Si5315 is based on Silicon Laboratories third-generation DSPLL® technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is user programmable, providing jitter performance optimization at the application level.

Features

â–  Provides jitter attenuation and frequency translation between SONET/PDH and Ethernet
â–  Supports ITU-T G.8262 Synchronous Ethernet equipment slave clock (EEC option 1 and 2) requirements with optional Stratum 3 compliant timing card clock source
â–  Two clock inputs/two clock outputs
■ Input frequency range: 8 kHz–644 MHz
■ Output frequency range: 8 kHz–644 MHz
■ Ultra low jitter: 0.23 ps RMS (1.875–20 MHz) 0.47 ps RMS (12 kHz–20 MHz)
â–  Simple pin control interface
â–  Selectable loop bandwidth for jitter attenuation: 60 to 8.4 kHz
â–  Automatic/Manual hitless switching and holdover during loss of inputs clock
â–  Programmable output clock signal format: LVPECL, LVDS, CML or CMOS
â–  40 MHz crystal or XO reference
â–  Single supply: 1.8, 2.5, or 3.3 V
â–  On-chip voltage regulator with high PSRR
â–  Loss of lock and loss of signal alarms
â–  Small size: 6 x 6 mm, 36-QFN
■ Wide temperature range: –40 to +85 ºC

Applications

â–  Synchronous Ethernet line cards
â–  SONET OC-3/12/48 line cards
â–  PON OLT/ONU
â–  Carrier Ethernet switches routers
â–  MSAN / DSLAM
â–  T1/E1/DS3/E3 line cards